This invention relates to output buffer circuits for semiconductor integrated circuit devices, and more particularly to a circuit having a low-voltage power supply and using N-channel output driver transistors.
In the manufacture of CMOS integrated circuit devices, as feature sizes continue to shrink, it has become necessary to reduce the power supply (e.g., to 3.3 V) in some devices to preclude damage due to hot carrier effects. However, it is still necessary to be able to interface to other chips using higher voltages (e.g., 5 V). The output buffer circuits employed in chips using 3.3 V supplies must therefore be able to withstand 5 V levels applied to the terminals of the chip. Three problems exist with traditional push-pull CMOS bi-directional output buffers when they are powered by a reduced power supply and, in the high-impedance output state (referred to as the Z-state), must receive higher levels. First, when a bi-directional output drives low coming out of the Z-state from an elevated voltage, an output NMOS pull-down transistor can suffer hot carrier effects. A commonly-used solution for this hot carrier problem is to cascode two NMOS devices (i.e., another N-channel transistor in series with the pull-down) with the gate of the top device biased to the reduced power supply. The second problem is that when a bi-directional output in Z-state is driven above the 3.3 V power supply by a diode drop (and hence the well bias), the drain junction diode of the output PMOS pull-up transistor will forward bias, injecting carriers into the well and posing potential reliability problems. And third, when the output in Z-state is driven a PMOS threshold drop above the reduced power supply, the output PMOS pull-up transistor will turn on, sinking current into the reduced power supply of the chip. Prior circuit techniques exist to solve the last two of these problems; however, they all pay a penalty in performance, chip area, and power due to added parasitics and increased gate area. One of these solutions is to isolate the PMOS pull-up transistor from the output node using a series NMOS transistor with the 3.3 V supply on its gate; this solution is undesirable since the PMOS pull-up device must be inordinately large to achieve acceptable performance. It is thus desirable to use an uncascoded NMOS pull-up transistor to eliminate the above encumbrances. However, an NMOS output pull-up would be subjected to gate oxide stress when, in Z-state, the gate of the NMOS output pull-up transistor is at zero volts and the output node is driven to 5 Volts. Also an output NMOS pull-up transistor would be subjected to body effect when driving and cannot, thus, drive to the 3.3 V rail. This poses the problem of adequate noise margin at Vo.sub.h for TTL levels.
An example of a CMOS output buffer circuit using a P-channel pull-up transistor is disclosed in my U.S. Pat. No. 4,963,766, assigned to Digital Equipment Corporation. This circuit is adapted to be powered by a low-voltage supply, e.g., 3.3 v., but yet is able to withstand higher voltages imposed on its output node. A P-channel pull-up transistor is employed, and the N-well of this pull-up transistor is connected to the higher-level voltage supply, e.g., 5.0-volts.
Another example of a CMOS output buffer circuit using a P-channel pull-up transistor is illustrated in U.S. Pat. No. 4,782,250. The N-well of the P-channel pull-up transistor is biased. An N-channel pass transistor in series with the N-channel pull-down device to avoid undue gate oxide stress on the pull-down when the output voltage exceeds the 3.3 V supply. Two cascoded P-channel devices are used for the pull-up. In Z-state, the gate of the P-channel transistor farthest from the pad and the N-well will track the output when the output exceeds the reduced power supply by V.sub.Tp.